FIELD OF THE INVENTION
The invention lies in the electronics field. More specifically, the invention relates to a method for testing an electronic circuit in which the actual state of circuit components which have previously been activated on a test basis after an initial initialization is compared with a setpoint state.
Such a method is, for example, the so-called scan method used in particular for testing integrated circuits.
Circuits that are enabled for testing in accordance with the scan method must be capable of being placed in a scan mode of operation in which selected circuit components, such as, for example, all the flip-flops of the circuit, are connected in such a way that they can be placed individually in specific initial states by means of a test device provided outside the circuit to be tested, and that their current state can, when necessary, be read out by the test device. This can be achieved when flip-flops are used as selected circuit components by virtue of the fact that the flip-flops are connected one behind the other in series in a scan mode of operation, the input terminal of a respective flip-flop being connected to the output terminal of the flip-flop located in front of it in series, and the output terminal of a respective flip-flop being connected to the input terminal of the flip-flop which comes after it in the series. Such an arrangement is also referred to as a scan chain.
Such a scan chain, to be more precise its elements formed by flip-flops in the example under consideration, can be initialized relatively easily. A signal applied to the input terminal of the first flip-flop of the scan chain, to be more precise the state of the relevant flip-flop which comes about in response thereto, is namely passed on from flip-flop to flip-flop with the clock of a clock signal applied to the flip-flops; with each clock pulse each flip-flop of the scan chain assumes the state of the flip-flop located in front of it in the scan chain.
If the x.sup.th flip-flop of the scan chain is placed in the state A, all that is necessary is "merely" to apply a signal to the input terminal of the first flip-flop of the scan chain. The signal places that flip-flop and the flip-flops connected downstream in the state A. Thereby, x clock pulses are applied to the scan chain (all the flip-flops of said chain).
Conversely, at the last flip-flop of the scan chain it is possible to read out the states of the individual flip-flops sequentially at a specific time.
If the scan chain contains n flip-flops, the circuit test is carried out according to the scan method as follows: firstly, the circuit is placed in the scan mode of operation, as a result of which the scan chain is formed. That scan chain is placed in a defined initial state by sequentially applying n input signals and n clock pulses. Then, the circuit is placed in a normal mode of operation; for this purpose the circuit is moved out of the scan mode of operation, the scan chain (the series connection of the flip-flops) is broken up. In the normal mode of operation, the circuit is briefly operated normally on a test basis. The time during which the circuit is operated normally is preferably defined by a number of clock cycles. This number of clock cycles is preferably very small (for example 1). In the time during which the circuit is operated normally, at least some of the states of the initially initialized flip-flops change, it being possible to determine from the way in which the circuit to be tested functions according to the regulations the (setpoint) state the flip-flops ought to be in at a respective time. After the circuit has operated normally for a predetermined number of clock cycles, it is returned to the scan mode of operation, as a result of which the flip-flops can be reconnected to form the scan chain. If the flip-flops which are connected in this way have clock signals applied to them in this state, data which represent the (actual) state of the flip-flops of the scan chain at the time when normal operation ends are pushed out sequentially at the end of the scan chain (from the output terminal of the last flip-flop of the scan chain) in time with the clock signals. If the actual state, determined as described, of the flip-flops of the scan chain is then compared with the known setpoint state of the chain, it is possible to determine whether or not the circuit to be tested is running without faults.
Tests that function in this way or similarly make it possible, in a relatively simple way, to test comprehensively even very complex circuits within a very short time. However, experience shows that under unfavorable conditions circuits which are functioning satisfactorily may be categorized as faulty. This is understandably a disadvantage which needs to be eliminated.